Simple VHDL / Verilog branch prediction on consumer CPUs.

Possible legal / technical issues (and solutions).

[Notice: thumbnail used with attribution: edu / fair use.]

This conversation with Assistant about simple branch prediction covers the basics and includes resources to help you produce VHDL / Verilog hash maps for branch prediction. [This post from SubStack allows all uses.]

“Branch instructions” are the compiled (bitcode) versions of if(condition) { function_q(); } else { function_w(); } or switch(integer) {case 1: function_q(); case 2: function_w();} clauses.
The most simple branch prediction just:

• Sets map[RIP] = target when a branch target is computed (RIP is the current instruction pointer on x86-64; different architectures have different monikers for this register).

• Prefetches map[RIP] when an old branch is added to the CPU’s “instruction pipeline”.

The use of such prefetches is:

• If condition is true twice in a row, the instructions for function_q() are prefetched into the “instruction pipeline” or “L1 cache”.

• Such prefetches prevent “pipeline stalls” (“pipeline stalls” occur if the CPU has to compute whether or not condition is true before the CPU can load the next instructions to execute. Unless the current instruction saturates all memory channels (most architectures have numerous), there is no cost to prefetch the next instructions while the current “pipeline” executes.)

Open-source Verilog hashmap: